Image processing circuit and method

ABSTRACT

An image processing circuit for eliminating noise from an image without lowering the actual resolution. The image contains input pixels, which include a processing subject pixel and proximal pixels located proximal to the processing subject pixel. Each input pixel has a pixel value. The image processing circuit includes a spatial filter for generating a filter value for the subject processing pixel based on the pixel values of the input pixels and first filter coefficients. A correction circuit compares the filter value with first and second limit values and corrects the filter value based on the comparison to generate a corrected filter value in a range between the first and second limit values. The image processing circuit eliminates noise from the image by correcting the pixel value of the processing subject pixel based on the corrected filter value.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2005-366969, filed on Dec. 20,2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to an image processing circuit and method,and more particularly, to a circuit and method for reducing noise in animage without lowering the actual resolution (visual perception ofresolution).

The quantity of pixels in imaging devices has been increasing over theyears. This has reduced the area of each pixel and lowered the signallevel (voltage, current) output by each pixel. As a result, thesignal-to-noise (S/N) ratio has decreased. Accordingly, it is desiredthat the noise in an image be decreased without the resolution beinglowered.

Japanese Laid-Open Patent Publication No. 2003-259126 describes a methodfor eliminating noise from image data with a spatial filter circuit. Thespatial filter circuit uses a coefficient table including pixel valuesof a plurality of pixels in a predetermined area (3×3) laid out about aprocessing subject pixel P11 (refer to FIG. 6A), the size correspondingto the predetermined area, and a coefficient table including a pluralityof filter coefficients K00 to K22 (refer to FIG. 6B). The spatial filtercircuit multiplies the pixel values of the pixels P00 to P22 by thefilter coefficients K00 to K22, respectively. Based on the products, thespatial filter circuit then calculates a filter value, which is employedas the pixel value for pixel P11. Each coefficient in the coefficienttable is set in accordance with a correction method.

A median filter is known as a spatial filter circuit. The median filtercompares the pixel values of a plurality of pixels, which are laid outin a predetermined area (3×3, 5×5, . . . ) about a processing subjectpixel P11, with one another. Then, the median filter sets the medianvalue of the pixel values as a filter value and employs the filter valueas the pixel value for the processing subject pixel P11.

SUMMARY OF THE INVENTION

In the prior art method, even if the computed filter value differsgreatly from the original pixel value of the processing subject pixel,the original pixel value is replaced by the filter value. This isperceived as blurring at edges of the original image or as a decrease inthe resolution of the original image. In other words, the noiseelimination of the prior art lowers the actual resolution of theoriginal image.

The present invention provides an image processing circuit and methodfor reducing noise without lowering the actual resolution.

One aspect of the present invention is an image processing circuit foreliminating-noise from an image. The image contains a plurality of inputpixels including a processing subject pixel and a plurality of proximalpixels located proximal to the processing subject pixel, with each inputpixel having a pixel value. The image processing circuit includes aspatial filter for generating a filter value for the subject processingpixel based on the pixel values of the input pixels and a plurality offirst filter coefficients. A correction circuit compares the filtervalue with a first limit value and a second limit value and correctingthe filter value based on the comparison result to generate a correctedfilter value in a range between the first limit value and the secondlimit value. The image processing circuit eliminates noise from theimage by correcting the pixel value of the processing subject pixelbased on the corrected filter value.

A further aspect of the present invention is an image processing methodfor eliminating noise from an image. The image contains a plurality ofinput pixels including a processing subject pixel and a plurality ofproximal pixels located proximal to the processing subject pixel, witheach input pixel having a pixel value. The method includes generating afilter value for the subject processing pixel with a spatial filterbased on the pixel values of the input pixels and a plurality of firstfilter coefficients, comparing the filter value with a first limit valueand a second limit value and correcting the filter value based on thecomparison result to generate a corrected filter value in a rangebetween the first limit value and the second limit value with acorrection circuit, and eliminating noise from the image by correctingthe pixel value of the processing subject pixel based on the correctedfilter value.

Other aspects and advantages of the present invention will becomeapparent from the following description, taken in conjunction with theaccompanying drawings, illustrating by way of example the principles ofthe invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with objects and advantages thereof, may best beunderstood by reference to the following description of the presentlypreferred embodiments together with the accompanying drawings in which:

FIG. 1 is a circuit diagram of an image processing circuit according toa first embodiment of the present invention;

FIG. 2A is an explanatory diagram of input image data;

FIG. 2B is an explanatory diagram of a coefficient table;

FIG. 3 is a circuit diagram of an image processing circuit according toa second embodiment of the present invention;

FIG. 4A is an explanatory diagram of input image data;

FIGS. 4B and 4C are explanatory diagrams of a coefficient table;

FIG. 5 is a circuit diagram of an image processing circuit according toa further embodiment of the present invention;

FIG. 6A is an explanatory diagram of input image data; and

FIG. 6B is an explanatory diagram of a coefficient table.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Image processing according to a first embodiment of the presentinvention will now be described.

Referring to FIG. 1, the image processing circuit of the firstembodiment includes a spatial filter circuit 11, which serves as aspatial filter. Pixel values of a predetermined number (e.g., 3×3) ofinput pixels P00 to P22 shown in FIG. 2A and a plurality of filtercoefficients (first filter coefficients) KOO to K22 of a coefficienttable T1 shown in FIG. 2B are input to the spatial filter circuit 11.The coefficient table T1 is stored in, for example, a storage devicesuch as a ROM, and the filter coefficients K00 to K22 are positive ornegative values. In FIG. 2A, pixel P11, which is located in the centerof input pixels P00 to P22, is the processing subject pixel. Further,pixels P00 to P02, P10, P12, and P20 to P22, which are located in theproximity of the pixel P11, are defined as proximal pixels. In thepreferred embodiment, the proximal pixels are adjacent to the processingsubject pixel.

The spatial filter circuit 11 includes multipliers 11 a, the quantity(e.g., nine) of which corresponds to the quantity of input pixels, andan adder 11 b, which is connected to the multipliers 11 a. Eachmultiplier 11 a multiplies the pixel value of the input pixel by thecorresponding filter coefficient and outputs the product (computationresult). For example, the leftmost multiplier 11 a in FIG. 1 multipliesthe pixel value of pixel P00 which is located at the upper left cornerin FIG. 2A, by the filter coefficient K00, which is located at the upperleft corner in FIG. 2B. The adder 11 b adds the products of every one ofthe multipliers 11 a to generate a filter value F11 for pixel P11. Thefilter value F11 is provided to a first comparator 12 and a firstselection circuit 13.

An upper limit value Vhi, which is stored beforehand in a storage deviceas a first limit value, is input to the first comparator 12. The upperlimit value Vhi is a positive value. The first comparator 12 comparesthe filter value F11 with the upper limit value Vhi and outputs acomparison result signal, which indicates whether or not the filtervalue F11 is greater than the upper limit value Vhi.

The filter value F1 and the upper limit value Vhi are input to the firstselection circuit 13. The first selection circuit 13 selectively outputseither one of the filter value F11 or the upper limit value Vhi inaccordance with the comparison result of the first comparator 12. Forexample, the first selection circuit 13 outputs the upper limit valueVhi when the filter value F11 is greater than the upper limit value Vhiand outputs the filter value F11 when the filter value F11 is notgreater than the upper limit value Vhi. The output value of the firstselection circuit 13 is input to the second comparator 14 and the secondselection circuit 15. The output value of the first selection circuit 13is input to a second comparator 14 and a second selection circuit 15.

A lower limit value Vlow, which is stored beforehand in a storage deviceas a second limit value, is input to the second comparator 14. The lowerlimit value Vlow is a negative value. The second comparator 14 comparesthe output value of the first selection circuit 13 with the lower limitvalue Vlow and outputs a comparison result signal, which indicateswhether or not the output value is less than the lower limit value Vlow.The first comparator 12 and the second comparator 14 cooperate toindicate the relationship of the filter value F11, the upper limit valueVhi, and the lower limit value Vlow in terms of level.

The output value of the first selection circuit 13 and the lower limitvalue Vlow are input to the second selection circuit 15. In accordancewith the comparison result of the second comparator 14, the secondselection circuit 15 selectively outputs either one of the output valueof the first selection circuit 13 or the lower limit value Vlow. Forexample, the selection circuit 15 outputs the lower limit value Vlowwhen the output value of the first selection circuit 13 is less than thelower limit value Vlow and outputs the output value of the firstselection circuit 13 when the output value of the first selectioncircuit 13 is not less than the lower limit value Vlow.

The first selection circuit 13, the second comparator 14, and the secondselection circuit 15 function as a correction circuit for correcting thefilter value F11 to a value included in a tolerable range between theupper limit value Vhi through the lower limit value Vlow. When thefilter value F11 is greater than the upper limit value Vhi, the upperlimit value Vhi is output from the correction circuit as a correctedfilter valued F11 a. When the filter value F11 is less than the lowerlimit value Vlow, the lower limit value Vlow is output from thecorrection circuit as the corrected filter valued F11 a. Otherwise, thefilter value F11 is output from the correction circuit as the correctedfilter value F11 a.

The pixel value of pixel P11 and the corrected filter value F11 a areprovided to an adder 16. The adder 16 adds the corrected filter valueF11 a to the pixel value of pixel P11 to generate and output a correctedpixel value Pd. The corrected pixel value Pd is stored as the pixelvalue for the processing subject pixel P11.

In comparison with the original pixel value of the pixel P11, noise isreduced in the pixel value Pd. The difference between the pixel value Pdand the original pixel value of pixel P11 ranges from the upper limitvalue Vhi, at the positive side, through the lower limit value Vlow, atthe negative side. In this manner, the difference between the pixelvalue Pd and the original pixel value of pixel P11 is restricted. Thisprevents the actual resolution of an image from decreasing. Thus,blurring does not occur at edges of an image.

The first embodiment has the advantages described below.

(1) The spatial filter circuit 11 generates the filter value from thepixel values of the input pixels P00 to P22, which include theprocessing subject pixel, and the filter coefficients K00 to K22. Thecorrection circuit, which includes the first comparator 12, the firstselection circuit 13, the second comparator 14, and the second selectioncircuit 15, corrects the filter value F11 to a value between the upperlimit value Vhi and the lower limit value Vlow. The corrected value isused to correct the original pixel value of the processing subject pixelP11. This eliminates noise and prevents the corrected pixel value fromdiffering greatly from the original pixel value. Thus, the actualresolution is prevented from being decreased.

(2) In an image processing circuit that adds the corrected filter valueF11 a to the pixel value of the pixel P11, which is the processingsubject, and generates a new, or corrected, pixel value, noise iseliminated and the actual resolution is prevented from being decreased.

An image processing according to a second embodiment of the presentinvention will now be discussed. Like or same reference numerals aregiven to those components that are the same or similar in the firstembodiment.

Referring to FIG. 3, an image processing circuit of the secondembodiment includes a first spatial filter circuit 11 and a secondspatial filter circuit 21. The first spatial filter circuit 11, which issubstantially identical to that of the first embodiment, generates afirst filter value F11 from pixel values of a predetermined number(e.g., 3×3) of input pixels P00 to P22 shown in FIG. 4A and a pluralityof filter coefficients (first filter coefficients) K00 to K22 of a firstcoefficient table T1 shown in FIG. 4B.

In the same manner as the first spatial filter circuit 11, pixel valuesof pixels P00 to P22 are input to the second spatial filter circuit 21.Further, second filter coefficients L00 to L22 of a second coefficienttable T2 shown in FIG. 4C are input to the spatial filter circuit 21.The second coefficient table T2 is stored in, for example, a storagedevice such as a ROM, and the filter coefficients L00 to L22 arepositive or negative values.

The second spatial filter circuit 21 includes multipliers 21 a, thequantity (e.g., nine) of which corresponds to the quantity of inputpixels, and an adder 21 b. Each multiplier 21 a multiplies the pixelvalue of the input pixel by the corresponding second filter coefficientand outputs the product (computation result). For example, the leftmostmultiplier 21 a in FIG. 3 multiplies the pixel value of pixel P00, whichis located at the upper left corner in FIG. 4A, by the second filtercoefficient L00, which is located at the upper left corner in FIG. 4C.The adder 21 b adds the products of every one of the multipliers 21 a togenerate a second filter value F21 for pixel P11. The second filtervalue F21 is provided to an absolute value computation circuit 22.

The absolute value computation circuit 22 computes the absolute value ofthe second filter value F21 and provides the absolute value as a firstlimit value, or an upper limit value Vhi, to a first comparator 12, afirst selection circuit 13, or a multiplier 23.

The multiplier 23 generates a lower limit value, which is a negativevalue. The multiplier 23 multiplies the output value of the absolutevalue computation circuit 22 by a negative fixed value “−1” to generatea lower limit value Vlow, which serves as a second limit value. Then,the multiplier 23 provides the lower limit value Vlow to the secondcomparator 14. The absolute value computation circuit 22 and themultiplier 23 function as a circuit for computing the upper limit valueand the lower limit value.

The image processing circuit of the second embodiment computes the upperand lower limit values of the first filter value F11 from the pixelvalues of the pixels P11 to P22 and the second filter coefficients L00to L22 of the second coefficient table T2.

The second filter coefficients L00 to L22 of the second coefficienttable T2 are set so that the second filter value F21 is small whensignificant or meaningful image information, such as an edge, isincluded near the processing subject pixel P11. If the differencebetween the pixel values P00 to P22 including the processing subjectpixel is small, that is, at meaningless image portions that are flat andhave no features, the second filter coefficients L00 to L22 are set sothat the second filter value P21 is large.

Accordingly, the image processing circuit dynamically varies thevariable range of the first filter value F11, that is, the upper andlower limit values of the first filter value F11, based on the pixelvalues of the processing subject pixel P11 and the proximal pixels(adjacent pixels) located in the proximity of the processing subjectpixel P11. Thus, the original image information is held at significantor meaningful image portions, and noise is effectively eliminated frommeaningless image portions that are flat and have no features.

In addition to the advantages of the first embodiment, the secondembodiment has the advantages described below.

(1) The second spatial filter circuit 21 generates the second filtervalue F21 for the processing subject pixel P11 based on the pixel valuesof the pixels P11 to P22 including the processing subject pixel and thesecond filter coefficients L00 to L22. The absolute value computationcircuit 22 computes the upper limit value Vhi based on the second filtervalue F21, and the multiplier 23 generates the lower limit value Vlowbased on the upper limit value Vhi. As a result, the upper limit valueVhi and the lower limit value Vlow are dynamically set in accordancewith the pixel values of the pixels P00 to P22. Thus, original imageinformation at significant portions may be held to prevent the actualresolution from being lowered.

It should be apparent to those skilled in the art that the presentinvention may be embodied in many other specific forms without departingfrom the spirit or scope of the invention. Particularly, it should beunderstood that the present invention may be embodied in the followingforms.

In the above embodiments, the spatial filter circuits 11 and 21 have aninput pixel quantity of 3×3 pixels. However, the quantity of the pixelssurrounding the processing subject pixel may be changed to, for example,5×5 or 7×7.

In the second embodiment, the computation circuit for setting the upperlimit value and the lower limit value is configured by the absolutevalue computation circuit 22 and the multiplier 23. However, thecomputation circuit 22 may be configured by a look-up table (LUT) 31 anda multiplier 23 (refer to FIG. 5).

In the second embodiment, the quantity of the input pixels in the firstspatial filter circuit 11 may differ from that of the second spatialfilter circuit 21.

In the second embodiment, the sign of the upper limit value is invertedto set the lower limit value. However, the upper and lower limit valuesmay be separately set. For example, the fixed value input to themultiplier 23 may be set to a value other than “−1”. Further, a thirdspatial filter circuit may be used, and an LUT used for reference may bechanged.

Other types of spatial filters, such as a versatile spatial filter or amedian filter, may be used. Further, the spatial filter is not limitedto hardware and may be software.

In the above embodiments, the filter value generated by the spatialfilter circuit 11 is added to the original pixel value of the pixel P11to generate the pixel value Pd, which is employed as the new pixel valueof the pixel P11. However, the present invention is not limited in sucha manner. For example, the original pixel value of the processingsubject pixel P11 may be replaced by the filter value generated by aspatial filter circuit, such as the output value of a second selectioncircuit. In this case, a first comparator compares the filter value witha value obtained by adding the upper limit value to the original pixelvalue, and a second comparator compares the output value of a firstselection circuit with a value obtained by adding the lower limit valueto the original pixel value.

The present examples and embodiments are to be considered asillustrative and not restrictive, and the invention is not to be limitedto the details given herein, but may be modified within the scope andequivalence of the appended claims.

1. An image processing circuit for eliminating noise from an image,wherein the image contains a plurality of input pixels including aprocessing subject pixel and a plurality of proximal pixels locatedproximal to the processing subject pixel, with each input pixel having apixel value, the image processing circuit comprising: a spatial filterfor generating a filter value for the subject processing pixel based onthe pixel values of the input pixels and a plurality of first filtercoefficients; and a correction circuit for comparing the filter valuewith a first limit value and a second limit value and correcting thefilter value based on the comparison result to generate a correctedfilter value in a range between the first limit value and the secondlimit value, the image processing circuit eliminating noise from theimage by correcting the pixel value of the processing subject pixelbased on the corrected filter value.
 2. The image processing circuitaccording to claim 1, further comprising: an adder for adding thecorrected filter value to the pixel value of the processing subjectpixel to generate a corrected pixel value of the processing subjectpixel.
 3. The image processing circuit according to claim 1, furthercomprising: a second spatial filter for generating a second filter valuefor the processing subject pixel based on the pixel value of theprocessing subject pixel, the pixel values of the plurality of proximalpixels, and a plurality of second filter coefficients; and a computationcircuit for computing the first limit value and the second limit valuebased on the second filter value.
 4. The image processing circuitaccording to claim 1, wherein the plurality of proximal pixels areadjacent to the processing subject pixel.
 5. The image processingcircuit according to claim 1, wherein the plurality of first filtercoefficients respectively correspond to the plurality of input pixels,the spatial filter including: a plurality of multipliers for multiplyingthe pixel values of the plurality of input pixels respectively by theplurality of first filter coefficients to generate a plurality ofproducts; and an adder, connected to the plurality of multipliers, foradding the products of the plurality of multipliers and generating thefilter value for the processing subject pixel.
 6. The image processingcircuit according to claim 5, wherein the plurality of input pixels, theplurality of first filter coefficients, and the plurality of multipliersare in quantities that are the same.
 7. An image processing method foreliminating noise from an image, wherein the image contains a pluralityof input pixels including a processing subject pixel and a plurality ofproximal pixels located proximal to the processing subject pixel, witheach input pixel having a pixel value, the method comprising the stepsof: generating a filter value for the subject processing pixel with aspatial filter based on the pixel values of the input pixels and aplurality of first filter coefficients; comparing the filter value witha first limit value and a second limit value and correcting the filtervalue based on the comparison result to generate a corrected filtervalue in a range between the first limit value and the second limitvalue with a correction circuit; and eliminating noise from the image bycorrecting the pixel value of the processing subject pixel based on thecorrected filter value.
 8. The image processing method according toclaim 7, wherein the step of eliminating noise from the image includes:adding the corrected filter value to the pixel value of the processingsubject pixel to generate a corrected pixel value for the processingsubject pixel.
 9. The image processing method according to claim 7,further comprising the steps of: generating a second filter value forthe processing subject pixel with a second spatial filter based on thepixel value of the processing subject pixel, the pixel values of theplurality of proximal pixels, and a plurality of second filtercoefficients; and computing the first limit value and the second limitvalue with a computation circuit based on the second filter value. 10.The image processing method according to claim 7, wherein the pluralityof proximal pixels are adjacent to the processing subject pixel.